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Efficient hardware controller synthesis for synchronous dataflow graph in system level design

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3 Author(s)
Hyunuk Jung ; Sch. of Comput. Sci. & Eng., Seoul Nat. Univ., South Korea ; Kangnyoung Lee ; Soonhoi Ha

Concerns automatic hardware synthesis from a data flow graph (DFG) specification in system-level design. In the presented design methodology, each node of a data flow graph represents a hardware library module that contains a synthesizable VHDL code. Our proposed technique automatically synthesizes a clever control structure, a cascaded counter controller, that supports asynchronous interaction with external modules while efficiently implementing the synchronous data flow semantics of the graph at the same time. Through comparison with previous work with some examples, the novelty of the proposed technique is demonstrated

Published in:

System Synthesis, 2000. Proceedings. The 13th International Symposium on

Date of Conference:

2000

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