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CA-CSTP: a new BIST architecture for sequential circuits

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4 Author(s)
Corno, F. ; Dipt. di Autom. e Inf., Politecnico di Torino, Italy ; Reorda, M.S. ; Squillero, G. ; Violante, M.

Circular Self-Test Path (CSTP) is an attractive technique for implementing BIST in sequential circuits; unfortunately, there are cases in which the fault coverage it attains is unacceptably low. This paper proposes a new architecture, named CA-CSTP, which overcomes these limitations and always reaches a high fault coverage by exploiting a slightly more complex chain cell based on a Cellular Automata architecture. Experimental results show the effectiveness of our proposal

Published in:

Test Workshop, 2000. Proceedings. IEEE European

Date of Conference:

2000