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Low cost concurrent test implementation for linear digital systems

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2 Author(s)
Bayraktaroglu, I. ; Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA ; Orailoglu, A.

An implementation of a low-cost, time-extended invariant-based concurrent test scheme for linear digital systems is presented. Both feedback and non-feedback systems are analyzed to identify gate and RT level implementation requirements for high on-line fault coverage. Simulation results on implementations satisfying the outlined requirements indicate that low latency, 100% on-line fault coverage is attained within hardware costs comparable to those of scan insertion

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Test Workshop, 2000. Proceedings. IEEE European

Date of Conference: