Cart (Loading....) | Create Account
Close category search window

Compressed bit fail maps for memory fail pattern classification

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)

This paper presents a new approach to configure compressed bit fail maps to allow fail pattern recognition. Construction of the special compression scheme is shown. This takes typical memory array fail patterns into account. Examples for different failure types are given. This scheme allows minimizing the necessary cache memory size for fail classification. A 64 Mbit fail map can be compressed to 2 k allowing classification of 13 fail types. Since cache RAM requirements are small, this scheme can be implemented in a manufacturing environment for all processed hardware. Compressed bit fail maps can be used to generate wafer and lot maps for diagnosis

Published in:

Test Workshop, 2000. Proceedings. IEEE European

Date of Conference:


Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.