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Multiprocessor parallel routing for the quality of service enabled Internet

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1 Author(s)
Shaowen Song ; Dept. of Phys. & Comput., Wilfrid Laurier Univ., Waterloo, Ont., Canada

This paper presents a parallel router and a packet switching mechanism by merging IPv6 and asynchronous transfer mode (ATM) as the protocol for the quality of service (QoS) enabled Internet. The hardware architecture of the parallel router consists of N-general-purpose computers each combined with a newly designed inter-node communication unit. This parallel architecture provides the necessary speed required in cell switching for real-time applications. The IPv6 packet and ATM cell co-switching mechanism implemented by the router controlling software preserves the connectionless future for non-real-time applications and provides the QoS for real-time applications, through merging the IPv6 and ATM protocols. The IPv6 packet and ATM cell co-routing/switch mechanism is developed for the current parallel router and is presented along with the parallel hardware architecture

Published in:

Parallel Computing in Electrical Engineering, 2000. PARELEC 2000. Proceedings. International Conference on

Date of Conference:

2000