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Implementation of an adaptive reconfigurable group organized (ARGO) parallel architecture

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2 Author(s)
L. Szajek ; Dept. of Electr. & Comput. Eng., Ryerson Polytech. Inst., Toronto, Ont., Canada ; L. G. Kirischian

The purpose of this paper is to demonstrate the implementation of an adaptable parallel architecture capable of system to task adaptation. The system implementation was based on XILINX FPGA devices. The adaptation was achieved by reconfiguring FPGAs to correspond to the task data flow graph. Scaling system resources and interconnecting them with a use of a virtual bus created clusters called group processors (GP). Each group processor operated as a fixed architecture system for the duration of the task. By developing custom macro operations such as vector processing units a speedup of as much as thirty times was obtained through hardware support and careful architecture selection. By developing multiple instances of macro-operations and combining them in GPs allowed efficient parallel processing

Published in:

Parallel Computing in Electrical Engineering, 2000. PARELEC 2000. Proceedings. International Conference on

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