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A novel procedure to evaluate design scalability based on device performance linked to photolithography data

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3 Author(s)
Karklin, L. ; Numerical Technol. Inc., San Jose, CA, USA ; Balasinski, A. ; Axelrad, V.

We propose a novel procedure to evaluate design manufacturability based on simulated photoresist patterns followed by extraction of MOSFET geometry and VT distribution. We demonstrate the procedure on a SRAM cell, to optimize photolithography for technology shrink from 0.16 to 0.13 /spl mu/m.

Published in:

Microprocesses and Nanotechnology Conference, 2000 International

Date of Conference:

11-13 July 2000