Referenced Items are not available for this document.
We propose a novel procedure to evaluate design manufacturability based on simulated photoresist patterns followed by extraction of MOSFET geometry and VT distribution. We demonstrate the procedure on a SRAM cell, to optimize photolithography for technology shrink from 0.16 to 0.13 /spl mu/m.
Published in:
Microprocesses and Nanotechnology Conference, 2000 International
Date of Conference: 11-13 July 2000
- Page(s):
- 10 - 11
- Meeting Date :
- 11 Jul 2000-13 Jul 2000
- Print ISBN:
- 4-89114-004-6
- INSPEC Accession Number:
- 6804645
- Conference Location :
- Tokyo, Japan
- Digital Object Identifier :
- 10.1109/IMNC.2000.872599
- Product Type:
- Conference Publications
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