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A low-jitter mixed-mode DLL for high-speed DRAM applications

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6 Author(s)
Jae Joon Kim ; Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea ; Sang-Bo Lee ; Tae-Sung Jung ; Chang-Hyun Kim
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This paper presents a salient clock deskewing method with a mixed-mode delay-locked loop (MDLL) for high-speed synchronous DRAM applications. The presented method not only solves the resolution problem of conventional digital deskewing circuits, but also improves the jitter performance to the level of well-designed analog deskewing circuits, while keeping the power consumption and locking speed of digital deskewing circuits. The whole deskewing circuit is fabricated in a 3.3-V 0.6-/spl mu/m triple-metal CMOS process and occupies a die area of 0.45 mm/sup 2/. Measured rms jitter is 6.38 ps. The power consumption of the entire chip, including I/O peripherals, is 33 mW at 200 MHz with a 3.3-V supply.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:35 ,  Issue: 10 )

Date of Publication:

Oct. 2000

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