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Browse Journals & Magazines > Computers, IEEE Transactions ...> Volume:37 Issue:11 Help

A multiple fault-tolerant processor network architecture for pipeline computing

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1 Author(s)
Tyszer, J. ; Comput. Center, Tech. Univ., Poznan, Poland

Certain fault-tolerant multiprocessor networks that can emulate linear array interconnections are considered. The system is fault tolerant of (m-1) node and link failures. One of the particularly attractive features of this network is that it allows for a linear array structure starting with any node even in spite of (m -2) faults. The configuration algorithm is fully distributed, and is performed on the basis of test results obtained from nonfaulty processors only. A simple fault identification procedure is developed using the above routing algorithm

Published in:
Computers, IEEE Transactions on  (Volume:37 ,  Issue: 11 )

Date of Publication: Nov 1988

Page(s):
1414 - 1418
ISSN :
0018-9340
INSPEC Accession Number:
3322584
Digital Object Identifier :
10.1109/12.8707
Date of Current Version :
06 August 2002
Issue Date :
Nov 1988
Sponsored by :
IEEE Computer Society

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