BF2 and boron double-implanted source/drain junctions for sub-0.25-μm CMOS technology

A double implant source/drain junction formation process using BF
₂
and boron is proposed for PMOSFET in sum-0.25-μm CMOS technology. Compared to the more conventional, single implant processes using BF
₂
, the double implant process with downscaled BF
₂
implant energy offers the advantages of lower junction capacitance, less boron penetration, thinner gate oxide, and wider process window, as experimentally demonstrated.