By Topic

VHDL-based digital circuit synthesis: a case study

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Viana, F.L. ; Fac. of Electr. & Comput. Eng., Univ. Estadual de Campinas, Sao Paulo, Brazil ; Damiani, F.

Present day computer-aided design of VLSI circuits calls for specifying the design at a sufficiently high level of abstraction. This approach allows the designers to describe systems in terms of a set of interacting components, which facilitates the reuse of subsystems in a complex design and reduces the design cycle. This paper describes a case study of the Description-and-Synthesis methodology for digital circuit design. Distinct digital addition algorithms were coded in VHDL and automatically synthesized using two different commercial Electronic Design Automation (EDA) environments. The resulting circuits were simulated and the overall results are shown and discussed

Published in:

Devices, Circuits and Systems, 2000. Proceedings of the 2000 Third IEEE International Caracas Conference on

Date of Conference:

2000