By Topic

Variations of interconnect capacitance and RC delay induced by process fluctuations

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
N. Shigyo ; Syst. LSI Design Div., Toshiba Corp., Yokohama, Japan

This article describes the influence of the process fluctuations such as the critical dimension (CD) variation on the interconnect capacitance C and RC delay. It is found that there is a tradeoff between C and RC delay variations because of the fringing capacitance. A new interconnect design guideline to reduce C and/or RC delay variations is proposed

Published in:

Statistical Metrology, 2000 5th International Workshop on

Date of Conference:

2000