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An efficient design for one-dimensional discrete Hartley transform using parallel additions

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1 Author(s)
Jiun-In Guo ; Dept. of Electron. Eng., Nat. Lien-Ho Inst. of Technol., Miao-Li, Taiwan

This paper presents a new efficient design for the one-dimensional (1-D) any-length discrete Hartley transform (DHT). Using a similar idea to the chirp-Z transform, an algorithm that can formulate the 1-D any-length DHT as cyclic convolutions is developed. This algorithm has higher flexibility in the transform length as compared with the existing approaches for prime length DHT or power-of-two DHT designs. Moreover, the proposed design exploits the cyclic convolution and uses parallel adders instead of multipliers in the hardware realization. The presented design not only possesses low hardware cost but also has low input/output (I/O) cost, high computing speeds, and flexibility in transform length

Published in:

Signal Processing, IEEE Transactions on  (Volume:48 ,  Issue: 10 )

Date of Publication:

Oct 2000

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