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Parametric compact models for flip chip assemblies

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5 Author(s)
Van Dooren, S. ; High Density Interconnection & Packaging Dept., IMEC, Heverlee, Belgium ; Vandevelde, B. ; Beyne, E. ; Christiaens, F.
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A parametric thermal compact modeling study of flip chip assemblies is presented. First, a star network of four thermal resistors was found to be optimal for a flip chip with arbitrary geometry and material properties. In a second step several parameters such as thermal underfill conductivity and die size were varied. The effect of these variations on the values of the four thermal resistors of the compact model is investigated. In a third step, a response surface model is derived from these compact models, which gives end-users the possibility of choosing a flip chip with arbitrary geometry and deduce automatically the corresponding thermal compact model. Having the compact model, it is now possible to apply customer specific boundary conditions to this compact model and compute the maximal temperature reached at the junction of the flip chip assembly in the specified environment

Published in:

Components and Packaging Technologies, IEEE Transactions on  (Volume:23 ,  Issue: 3 )

Date of Publication:

Sep 2000

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