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A low voltage embedded single port SRAM generator in a 0.18 μm standard CMOS process

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5 Author(s)
C. Frey ; ST Microelectron., Crolles, France ; F. Genevaux ; C. Issartel ; D. Turgis
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A low voltage embedded single port SRAM memory generator implemented in a 6 metals, 0.18 μm standard CMOS process is described. The typical (8k×16) cut achieves 300 MHz maximum frequency, with a 3.3 ns access time at 1.3 V and 25°C and a typical power of 60 μA/MHz at 1.3 V. Special care has been taken to reduce the standby current as well. The hierarchical wordline architecture, and a differential output bus allow low power characteristics. At the same time high speed is reached, especially thanks to a novel dynamic wordline decoder. The generator ranges from 1 Kbit to 2 Mbit and features an optional programmable redundancy

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Memory Technology, Design and Testing, 2000. Records of the 2000 IEEE International Workshop on

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