By Topic

66 MHz 2.3 M ternary dynamic content addressable memory

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

7 Author(s)
Lines, V. ; Mosaid Technol. Inc., USA ; Ahmed, A. ; Ma, P. ; Ma, S.
more authors

This paper describes a 66 MHz 2.3 M Content Addressable Memory (CAM) which uses DRAM technology for the basic ternary CAM cell. The chip's architecture allows a high speed search operation and single cycle learning. The DRAM based cell structure enables implementation of a larger table size than is available in similar technology SRAM based CAMs. A new matchline sense amplifier allows fast, low power sensing of the matchline. Among the chip's many features are a DDR input interface and the ability to cascade up to eight parts without additional logic. The density and speed of this part make it suitable for many applications such as network switching

Published in:

Memory Technology, Design and Testing, 2000. Records of the 2000 IEEE International Workshop on

Date of Conference:

2000