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Yield analysis methodology for low defectivity wafer fabs

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1 Author(s)
Rajkanan, K. ; KLA-Tencor Corp., Milpitas, CA, USA

It is well known that the yield of an integrated circuit can be modeled based on random defect density. In state-of-the-art wafer fabs, continuous defect reduction is a high engineering priority, and as a result they indeed achieve entitlement values for the defect density, as determined by the design rules, equipment set, and their facility characteristics. Even if a wafer fab achieves its entitlement defect density, a comprehensive yield analysis methodology is still required not only to identify any yield excursions, but also to continually find ways for further yield improvements. Whereas in a wafer fab with defect density above its entitlement value, the yield analysis methodology can easily be focussed on defect density reduction alone, in the low defectivity wafer fabs different approach needs to be adopted. In this paper we discuss yield analysis methodologies appropriate for low defectivity wafer fabs

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Memory Technology, Design and Testing, 2000. Records of the 2000 IEEE International Workshop on

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