By Topic

Optimizing memory tests by analyzing defect coverage

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Jee, A. ; HPL Inc., San Jose, CA, USA ; Colburn, J.E. ; Irrinki, V.S. ; Puri, M.

This paper describes how analyzing the defect coverage of memory tests can lead to optimized test coverage and rest application time before the device reaches production. A 9-port embedded SRAM will be used as the example memory for this paper. We will analyze four different functional tests and show that using just two of the four tests provides nearly all the defect coverage of all four tests, but requires a fraction of the test application time. We will also show that a more complete test set should contain non-simultaneous port accesses and time-dependent tests

Published in:

Memory Technology, Design and Testing, 2000. Records of the 2000 IEEE International Workshop on

Date of Conference: