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A CMOS buffer without short-circuit power consumption

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1 Author(s)
Changsik Yoo ; Integrated Syst. Lab., Swiss Fed. Inst. of Technol., Zurich, Switzerland

A new CMOS buffer without short-circuit power consumption is proposed. The gate-driving signal of the output pull-up (pull-down) transistor is fed back to the output pull-down (pull-up) transistor to get tri-state output momentarily, eliminating the short-circuit power consumption, The HSPICE simulation results verified the operation of the proposed buffer and showed the power-delay product is about 15% smaller than conventional tapered CMOS buffer

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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on  (Volume:47 ,  Issue: 9 )