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Inserting scan at the behavioral level

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3 Author(s)
Aktouf, C. ; Nat. Polytech. Inst., Grenoble, France ; Fleury, H. ; Robach, C.

This article presents a method for inserting test logic at the behavioral level of a VHDL design description. The method is easy to use, and in most cases it requires lower area overhead than classical scan insertion methods

Published in:

Design & Test of Computers, IEEE  (Volume:17 ,  Issue: 3 )