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Circuit design challenges for high-speed CMOS continuous-time switched-current ΣΔ modulators

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3 Author(s)
L. Luh ; Univ. of Southern California, Los Angeles, CA, USA ; J. Choma ; J. Draper

This paper discusses circuit design problems when implementing low-pass CMOS continuous-time switched-current ΣΔ modulators for high-speed operation or wide-bandwidth conversion. These problems cause difficulties when certain high-performance architectures are intended to be used for improving performance, such as multi-bit quantizer, cascade structure, high-order single loop structure, and parallelism. These problems arise mainly as a result of an uncertain transfer function, an extra loop delay, and/or mismatching among integrator capacitors of the modulator. These problems will be discussed to explore the limitation when more advanced architectures are applied

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Circuits and Systems, 1999. 42nd Midwest Symposium on  (Volume:1 )

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