By Topic

Circuit design challenges for high-speed CMOS continuous-time switched-current ΣΔ modulators

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
L. Luh ; Univ. of Southern California, Los Angeles, CA, USA ; J. Choma ; J. Draper

This paper discusses circuit design problems when implementing low-pass CMOS continuous-time switched-current ΣΔ modulators for high-speed operation or wide-bandwidth conversion. These problems cause difficulties when certain high-performance architectures are intended to be used for improving performance, such as multi-bit quantizer, cascade structure, high-order single loop structure, and parallelism. These problems arise mainly as a result of an uncertain transfer function, an extra loop delay, and/or mismatching among integrator capacitors of the modulator. These problems will be discussed to explore the limitation when more advanced architectures are applied

Published in:

Circuits and Systems, 1999. 42nd Midwest Symposium on  (Volume:1 )

Date of Conference:

1999