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Device simulation of SOI MOSFET's has several difficulties originating from the floating body features. One of them is numerical instability of the solution of carrier densities in channel region due to the floating body effect, which is unlike the conventional MOSFET's. Another problem is physical possibility of multiple solutions even at the same bias condition, which results in the hysteresis characteristics such as Single-Transistor Latch (STL) phenomena. To improve robustness of SOI simulation, we have developed a Quasi-Transient (QT) method for static (DC) mode analysis, and showed that fast and stable DC analysis is realized in device simulation of SOI MOSFET's. In this paper, we show that the STL phenomena of SOI MOSFET's are successfully simulated with the QT method for analysing floating body and parasitic bipolar effects of thin-film SOI devices.