By Topic

An open architecture for next generation space onboard processing

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Harris, M. ; Sanders Associates Inc., Nashua, NH, USA ; Ngo, D.

An advanced, scalable, standards-based high performance computer architecture, derived from DARPA High Performance Computing research, and adapted for space on-board processing is presented. Networked multicomputing achieves supercomputing performance by combining low cost, high performance, highly integrated single chip microprocessors and high bandwidth inter-processor network fabrics. To achieve high processing efficiency, a two level multicomputer isolates the application processing resource from the communication and control layer. Here we present a two level space on-board processor architecture in which the communication and control layer of the multiprocessor has been allocated functions essential to achieve required survivability and reliability for space applications

Published in:

Digital Avionics Systems Conference, 1999. Proceedings. 18th  (Volume:2 )

Date of Conference: