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In this paper, we demonstrate how the true single-phase clocking (TSPC) circuit technique is utilized fur a high-speed recursive filter application, with a high degree of design automation. This features a quick netlist generation of integral high-speed arithmetic modules, utilization of carry-save architectures, and synthesis and optimization with a TSPC cell library. Implementation results in a 0.8 /spl mu/m standard CMOS process indicate substantial performance improvements over traditional designs, at the same time keeping design time very short. Fabricated samples of the third-order lattice wave digital filter were measured at 265 Msamples/s, which is more than double the sample rate reported in previous works on the same filter and same or comparable technology.