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Peak power estimation of VLSI circuits: new peak power measures

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3 Author(s)
M. S. Hsiao ; Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA ; E. M. Rudnick ; J. H. Patel

New measures of peak power are proposed in the context of sequential circuits, and an efficient automatic procedure is presented to obtain very good lower bounds on these measures, as well as providing the actual input vectors that attain such bounds. Automatic generation of a functional vector loop for near-worst case power consumption is also attained. Experiments show that vector sequences generated give much more accurate estimates of peak power dissipation and are generated in significantly shorter execution times than estimates made from randomly generated sequences for four delay models.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:8 ,  Issue: 4 )