By Topic

HDL presynthesis optimizations using a tabular model

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Jian Li ; Cisco Syst., San Jose, CA, USA ; R. K. Gupta

In this paper, we introduce presynthesis optimizations on hardware description languages (HDLs). Presynthesis optimizations consist of two categories of tasks: 1) source-level transformations, which produce optimized behavioral HDL descriptions that lead to improved synthesis results and 2) source-level analysis, which produces information useful in the synthesis stage to improve the quality of the synthesized circuits. Presynthesis optimizations are carried out on an intermediate tabular representation called timed decision table (TDT). We have implemented the TDT-based presynthesis optimization algorithms in a software package called Pumpkin. Experiments running Pumpkin on named benchmarks show promising results.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:8 ,  Issue: 4 )