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Reduction of source/drain series resistance and its impact on device performance for PMOS transistors with raised Si/sub 1-x/Gex source/drain

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6 Author(s)
Hsiang-Jen Huang ; Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Kun-Ming Chen ; Chun-Yen Chang ; Liang-Po Chen
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P-channel MOS transistors with raised Si/sub 1-x/Ge/sub x/ and Si source/drain (S/D) structure selectively grown by ultra high vacuum chemical vapor deposition (UHVCVD) were fabricated for the first time. The impact of Si/sub 1-x/Ge/sub x/ and Si epitaxial S/D layers on S/D series resistance and drain current of p-channel transistors were studied. Our results show that devices with the raised Si/sub 1-x/Ge/sub x/ S/D layer display only half the value of the specific contact resistivity and S/D series resistance (R/sub SD/), compared with those with a Si raised S/D layer. The improvement is even more dramatic when comparing with conventional devices without any raised S/D layer, i.e., R/sub SD/ of devices with Si/sub 1-x/Ge/sub x/ raised S/D is only about one fourth that of conventional devices. Moreover, the raised SiGe S/D structure produces a 29% improvement in transconductance (g/sub m/) at an effective channel length of 0.16 μm. These performance improvements, together with several inherent advantages, such as self-aligned selective epitaxial growth (SEG) and the resultant T-shaped gate structure, make the new device with raised Si/sub 1-x/Ge/sub x/ S/D structure very attractive for future sub-0.1 μm p-channel MOS transistors.

Published in:

IEEE Electron Device Letters  (Volume:21 ,  Issue: 9 )