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A comparison of three rounding algorithms for IEEE floating-point multiplication

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2 Author(s)
Even, G. ; Dept. of Electr. Eng. Syst., Tel Aviv Univ., Israel ; Seidel, P.-M.

A new IEEE compliant floating-point rounding algorithm for computing the rounded product from a carry-save representation of the product is presented. The new rounding algorithm is compared with the rounding algorithms of Yu and Zyner (1995) and of Quach et al. (1991). For each rounding algorithm, a logical description and a block diagram is given, the correctness is proven, and the latency is analyzed. We conclude that the new rounding algorithm is the fastest rounding algorithm, provided that an injection (which depends only on the rounding mode and the sign) can be added in during the reduction of the partial products into a carry-save encoded digit string. In double precision format, the latency of the new rounding algorithm is 12 logic levels compared to 14 logic levels in the algorithm of Quach et al. and 16 logic levels in the algorithm of Yu and Zyner

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Computers, IEEE Transactions on  (Volume:49 ,  Issue: 7 )