Multi-user detection in spread-spectrum communications involves repeatedly solving a system of equations to decouple multiple-access interference among users communicating with a basestation. This paper proposes a vector multiprocessor to provide the necessary computing performance. Two vector processors with parallel vector pipelines that are optimized for vector multiply-add operations achieve sustained gigaflop-level performance with a 100 MHz internal clock. Performance analysis of vector assembly-language code on eight vector units indicates that matrix-vector multiplication for a 32×32 problem can be performed in less than 2 μs, and that matrix inversion can be performed in less than 200 μs
Published in:
Application-Specific Systems, Architectures, and Processors, 2000. Proceedings. IEEE International Conference on
Date of Conference: 2000