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Performance-scalable array architectures for modular multiplication

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2 Author(s)
Freking, W.L. ; Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA ; Parhi, K.K.

Modular multiplication is a fundamental operation in numerous public-key cryptosystems including the RSA method. The increasing popularity of Internet e-commerce and other security applications translate into a demand for a scalable performance hardware design framework. Previous scalable hardware methodologies either were not systolic and thus involved performance-degrading, full-word-length broadcasts or were not scalable beyond linear array size. In this paper these limitations are overcome with the introduction of three scalable-performance modular multiplication architectures based on systolic arrays. Very high clock rates are feasible, since the cells composing the architectures are of bit-level complexity. Architectural methods based on both binary and high-radix modular multiplication are derived. All techniques are constructed to allow additional flexibility for the impact of interconnect delay within the design environment

Published in:

Application-Specific Systems, Architectures, and Processors, 2000. Proceedings. IEEE International Conference on

Date of Conference:

2000