Minimal complexity hierarchical loop representations of SFG processors for optimal high level synthesis

In order to rapidly produce, using high level synthesis, quality silicon implementations of Signal Flow Graphs (SFGs) for large size, real-world signal/image processing problems, the Hardware Description Language (HDL) representations of SFG nodes should possess certain desirable characteristics. We have embedded in DG2VHDL, a design tool developed by the authors which translates automatically an algorithm's Dependence Graph into synthesizable VHDL models for SFG arrays, an algorithm that formulates the minimal design complexity nested loop structure (to be defined herein) for each SFG processor. This representation will, in all but some pathological cases, produce post-synthesis hardware whose area scales near optimally with increasing problem size. Furthermore, the time and memory required for the synthesis of such models does not increase with the problem size. A polynomial time heuristic is presented which finds (almost always) the minimal design complexity loop representation of SFG nodes