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Clock and data recovery circuit with two exclusive-OR phase frequency detector

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2 Author(s)
Dong-Hee Kim ; Dept. of Electr. & Comput. Eng., Inha Univ., Inchon, South Korea ; Jin-Ku Kang

A clock and data recovery circuit with a two exclusive-OR phase-frequency detector is proposed. The PFD generates the control signal for the voltage-controlled oscillator (VCO) in the phase-locked loop by comparing different phase clocks and input data. Simulations show that this circuit operates an input at data rate of 800 Mbit/s to 1.2 Gbit/s under 2.5 V using 0.25 μm CMOS technology

Published in:

Electronics Letters  (Volume:36 ,  Issue: 16 )

Date of Publication:

3 Aug 2000

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