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An on-chip clock-adjusting circuit with sub-100-ps resolution for a high-speed DRAM interface

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5 Author(s)
Noda, H. ; Semicond. & IC Group, Hitachi Ltd., Tokyo, Japan ; Aoki, M. ; Tanaka, H. ; Nagashima, O.
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A novel fully digital fine-delay circuit for a high-speed DRAM interface is proposed. The circuit consists of arrayed delay components and generates a group of rail-to-rail delayed signals with sub-100-ps resolution. The input-coupling element (squeezer) in the delay component converges the variations of the resolution. A test device design using 0.35-μm technology demonstrates that a resolution of 26 ps can be achieved. A clock-recovery circuit using this circuit has a two-clock-cycle lock time and sub-100-ps error

Published in:

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on  (Volume:47 ,  Issue: 8 )

Date of Publication:

Aug 2000

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