By Topic

High-speed interconnect schemes for a pipelined FPGA

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Lee, H.J. ; Dept. of Electr. Eng., Stanford Univ., CA, USA ; Flynn, M.J.

The paper presents two high-speed interconnect schemes for a pipelined FPGA utilising a locally synchronised postcharging technique. By avoiding a global synchronised clock, we reduce the power consumption significantly. Through postcharging the interconnect and overlapping the postcharging delay with the logic delay, we successfully hide the postcharge time. The long channel devices significantly reduce the area penalty due to delay elements. The timing simulation is done using Hspice for a TSMC 0.35 μm and area is measured by drawing key elements in MAGIC and using the area model developed by Betz. The postcharge scheme shows a 30% delay reduction over the precharge scheme and up to 310% and 230% delay reductions over the conventional NMOS pass transistor scheme and the tristate buffer scheme respectively

Published in:

Computers and Digital Techniques, IEE Proceedings -  (Volume:147 ,  Issue: 3 )