Methods of exploiting simulation technology for simulating the timing of dynamically reconfigurable logic

In a dynamically reconfigurable design, the logic on the FPGA changes over time. The operation of each distinct combination of circuits that can be active on a device simultaneously must be functionally verified. The dynamic transitions between different circuit combinations must also be functionally verified. After successful verification, a unique floorplan must be created for each of the circuit combinations by the physical design tools. The detailed timing information derived for each floorplan must be back-annotated and the circuit combinations must be individually reverified with the accurate timing information. The physical design tools must place and route dynamically reconfigurable circuits that share common areas of the device array. A technique for functionally verifying dynamically reconfigurable designs, called Dynamic Circuit Switching (DCS), has been reported previously. The paper presents new techniques that make the simulation of dynamically reconfigurable logic with back-annotated timing possible for the first time. It also describes DCSTech, a CAD tool that automates these techniques. DCSTech works in conjunction with an enhanced version of DCS, called DCSim. The new design techniques provide the core of a design flow for dynamically reconfigurable logic. The new CAD tools, together with others reported previously, constitute an emerging CAD framework that automates the new design flow