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Compact VLSI neural network circuit with high-capacity dynamic synapses

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4 Author(s)
Yoondong Park ; Center for Neural Eng., Univ. of Southern California, Los Angeles, CA, USA ; Liaw, J.-S. ; Sheu, B.J. ; Berger, T.W.

Low-power low-voltage mixed-analog/digital-signal CMOS technology is used in implementing a novel dynamic-synapse neural network microchip. A basic building block for dynamic process is implemented with a variable current source, resistors, charging/discharging capacitances, and transmission gates. It was designed and simulated in 0.35 μm technology. The dynamic synapse function is implemented with resistor-capacitor exponential circuits, analog summing circuit, voltage comparator with hysteresis, and digital logic block. A neural network system with six input neurons, two output neurons, and 18 synapses is designed. Each neuron and dynamic synapse has individual threshold and gain. The circuit was simulated with two different input pulses to evaluate feedback inhibitory pulses, each action potential, and EPSP (excitatory post synaptic potential) of each dynamic processing point. Simulation results show that this dynamic synapse can be used for advanced neural processing including speech recognition application

Published in:

Neural Networks, 2000. IJCNN 2000, Proceedings of the IEEE-INNS-ENNS International Joint Conference on  (Volume:4 )

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