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MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications

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6 Author(s)
Singh, H. ; Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA ; Ming-Hau Lee ; Guangming Lu ; Kurdahi, F.J.
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This paper introduces MorphoSys, a reconfigurable computing system developed to investigate the effectiveness of combining reconfigurable hardware with general-purpose processors for word-level, computation-intensive applications. MorphoSys is a coarse-grain, integrated, and reconfigurable system-on-chip, targeted at high-throughput and data-parallel applications. It is comprised of a reconfigurable array of processing cells, a modified RISC processor core, and an efficient memory interface unit. This paper describes the MorphoSys architecture, including the reconfigurable processor array, the control processor, and data and configuration memories. The suitability of MorphoSys for the target application domain is then illustrated with examples such as video compression, data encryption and target recognition. Performance evaluation of these applications indicates improvements of up to an order of magnitude (or more) on MorphoSys, in comparison with other systems

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Computers, IEEE Transactions on  (Volume:49 ,  Issue: 5 )