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Latch-up characterization using novel test structures and instruments

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6 Author(s)
Cane, C. ; Centre Nacional de Microelectronica, Campus Univ. Autonoma de Barcelona, Bellaterra, Spain ; Lozano, M. ; Cabruja, E. ; Anguita, J.
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A test structure for quickly determining the latch-up sensitivity of different geometries and the technological solutions in CMOS processes is presented. The structure permits the measurement of triggering and holding voltages with a simple oscilloscope and a voltage source. The device consists of an integrated astable oscillator (based on a p-n-p-n structure) that must be characterized. The good behavior of the measurement set-up is demonstrated by designing, fabricating and characterizing the latch-up of two different CMOS technologies using the test structure and instruments. Furthermore, the use of simple digitizing oscilloscopes facilitates obtaining statistical latch-up data

Published in:

Semiconductor Manufacturing, IEEE Transactions on  (Volume:4 ,  Issue: 3 )

Date of Publication:

Aug 1991

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