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VLSI systolic array architecture for the lattice structure of the discrete wavelet transform

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2 Author(s)
Reyes, C.E.C. ; Dept. of Electron. & Comput. Eng., Santiago de Compostela Univ., Spain ; Bruguera, J.D.

This paper presents a regular, fast, area-efficient and parallelizable architecture for the computation of the one dimensional discrete wavelet transform (DWT). This architecture is based on the lattice structure for wavelet filters, from which, using regularization and linear space-time mapping techniques, we deduce a general systolic array applicable to any number of decomposition levels. Next we show that each processor of the array can be parallelized in a simple and direct form, an advantage that, in addition to those pertaining to the lattices and the systolic arrays, make this an attractive alternative for the implementation in VLSI and/or in a distributed network

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Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on  (Volume:4 )

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