By Topic

A ultra high speed clock distribution technique using a cellular oscillator network

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Sungkil Hwang ; Div. of Electron. Eng., Hallym Univ., Chunchon, South Korea ; Gyu Moon

This paper describes a novel process-gradient insensitive GHz clock distribution technique using a Cellular Oscillator Network. With its inherent structural synchronous characteristics, the Cellular Oscillator Network can be used in microprocessors or high-speed digital logic, where ultra high speed clock distribution with picosecond order clock skew is inevitably needed. A sleeping mode technique is also presented for power minimization. This new technique is simulated and proved with typical 3 V, 0.8 μm CMOS N-well process parameters

Published in:

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on  (Volume:4 )

Date of Conference:

2000