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A ultra high speed clock distribution technique using a cellular oscillator network

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2 Author(s)
Sungkil Hwang ; Div. of Electron. Eng., Hallym Univ., Chunchon, South Korea ; Gyu Moon

This paper describes a novel process-gradient insensitive GHz clock distribution technique using a Cellular Oscillator Network. With its inherent structural synchronous characteristics, the Cellular Oscillator Network can be used in microprocessors or high-speed digital logic, where ultra high speed clock distribution with picosecond order clock skew is inevitably needed. A sleeping mode technique is also presented for power minimization. This new technique is simulated and proved with typical 3 V, 0.8 μm CMOS N-well process parameters

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Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on  (Volume:4 )

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