Scalable interconnection networks for partial column array processor architectures

In parallel architectures for discrete trigonometric transforms, the number of processing elements is typically dependent on the transform size. Scalable architectures can be constructed with a partial column approach where the computation is performed iteratively with less number of processing elements. This approach results in a need for complex data reordering for realizing the interconnections between the processing columns. In this paper, such interconnection networks performing temporal and spatial reordering are proposed. These networks realize the data reordering found in constant geometry radix-2/sup r/ algorithms, which exist, e.g., for discrete Fourier, sine, cosine, and Hartley transforms. A general decomposition of stride by 2/sup r/ permutation is shown with corresponding network implementations. Furthermore, modifications to support mixed-size and 2-D transforms are discussed.