By Topic

Scalable interconnection networks for partial column array processor architectures

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Takala, J. ; Digital & Comput. Syst. Lab., Tampere Univ. of Technol., Finland ; Akopian, D. ; Astola, J. ; Saarinen, J.

In parallel architectures for discrete trigonometric transforms, the number of processing elements is typically dependent on the transform size. Scalable architectures can be constructed with a partial column approach where the computation is performed iteratively with less number of processing elements. This approach results in a need for complex data reordering for realizing the interconnections between the processing columns. In this paper, such interconnection networks performing temporal and spatial reordering are proposed. These networks realize the data reordering found in constant geometry radix-2r algorithms, which exist, e.g., for discrete Fourier, sine, cosine, and Hartley transforms. A general decomposition of stride by 2 r permutation is shown with corresponding network implementations. Furthermore, modifications to support mixed-size and 2-D transforms are discussed

Published in:

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on  (Volume:4 )

Date of Conference: