A set of novel techniques are implemented in a CAD tool, FASTEST, which achieves more than one order of magnitude CPU time reduction in typical statistical electrical evaluation of AC and now transient and DC specifications of analog circuits, A description of techniques for DC specifications is presented herein. The tool performance is demonstrated via the analysis of a multiple current mirror. The CPU time is reduced by one order of magnitude with respect to conventional Monte Carlo simulation, while maintaining similar accuracy in the computations
Published in:
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
(Volume:4
)
Date of Conference: 2000