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An efficient design for one dimensional discrete cosine transform using parallel adders

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1 Author(s)
Jiun-In Guo ; Dept. of Electron. Eng., Nat. Lien-Ho Inst. of Technol., Miao-Li, Taiwan

This paper proposes an efficient parallel adder based design for 1-D any-length discrete Cosine transform (DCT). Using the similar idea to the Chirp-Z transform, we develop an algorithm formulating the 1-D any-length DCT as cyclic convolutions. The proposed design using this algorithm not only owns higher flexibility in the transform length, but also possesses low hardware cost by using the parallel adder implementation. Considering an example using 16-bits coefficients, the proposed design can save much gate area as compared with other designs in the longer transform length applications

Published in:

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on  (Volume:5 )

Date of Conference:

2000

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