By Topic

An efficient design for one dimensional discrete cosine transform using parallel adders

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Jiun-In Guo ; Dept. of Electron. Eng., Nat. Lien-Ho Inst. of Technol., Miao-Li, Taiwan

This paper proposes an efficient parallel adder based design for 1-D any-length discrete Cosine transform (DCT). Using the similar idea to the Chirp-Z transform, we develop an algorithm formulating the 1-D any-length DCT as cyclic convolutions. The proposed design using this algorithm not only owns higher flexibility in the transform length, but also possesses low hardware cost by using the parallel adder implementation. Considering an example using 16-bits coefficients, the proposed design can save much gate area as compared with other designs in the longer transform length applications

Published in:

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on  (Volume:5 )

Date of Conference: