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VLSI design of Reed-Solomon decoder architectures

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3 Author(s)
Hanho Lee ; Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA ; Meng-Lin Yu ; Leilei Song

This paper presents VLSI implementations of an 8-error correcting (255, 239) Reed-Solomon (RS) decoder architecture for the optical fibre systems. We present the RS decoders using Euclidean and modified Euclidean algorithms which are regular and simple, and naturally suitable for VLSI implementation. We investigate hardware complexity, clock frequency and data processing rate for those RS decoders. The RS decoder based on the modified Euclidean algorithm operates at a clock frequency of 75 MHz and has a data processing rate of 600 Mbits/s in 0.25-μm CMOS technology with a supply voltage of 2.5 V

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Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on  (Volume:5 )

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