By Topic

Digital correction of circuit imperfections in cascaded Σ-Δ modulators composed of 1st-order sections

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Davis, A.J. ; Rhode Island Univ., Kingston, RI, USA ; Fischer, G. ; Hans-Helge, A. ; Hess, J.

An approach to remove the effects of amplifier finite gain and C-ratio mismatches in the 1-1-1 (MASH) and the 1-1-1-1 cascaded sigma-delta modulator is presented. By correcting the digital outputs with estimates of the parasitic errors due to analog circuit imperfections, uncancelled quantization noise terms can be removed. A 1-1-1-1 cascaded modulator, implemented as a fully differential switched-capacitor circuit, has been fabricated in a 1.2 μm, double-poly, n-well CMOS process. Measurements of the modulator verify that for an amplifier gain of 60 dB, C-ratio mismatch errors of 0.52% and 0.054%, the error correction offers an overall improvement in SNDR of 12-22 dB. A 12 μVrms sine wave can be restored with a positive SNDR

Published in:

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on  (Volume:5 )

Date of Conference:

2000