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A high speed low power CMOS clock driver using charge recycling technique

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3 Author(s)
Bouras, I. ; Inst. of Microelectron., NCSR Demokritos, Greece ; Liaperdos, Y. ; Arapoyanni, A.

This paper presents an Improved Power-Delay Product (PDP) CMOS clock driver based on the charge recycling technique. Two NMOS pass transistors driven by appropriate control signals are used to accomplish the charge recycling procedure. Simulations have shown an up to 18% improvement of PDP over an equivalent conventional CMOS driver

Published in:

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on  (Volume:5 )

Date of Conference:

2000