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A novel VLSI architecture for Lempel-Ziv based data compression

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2 Author(s)
Yeong-Kang Lai ; Dept. of Comput. Sci. & Inf., Nat. Dong-Hua Univ., Taiwan ; Kuo-Chen Chen

In this paper, a novel VLSI architecture for Lempel-Ziv-based data compression/decompression is presented. Based on the efficient data flow, the proposed architecture can fully exploit the data-reuse to decrease external memory accesses and reduce the pin count. In addition, parameters of the architecture such as the sliding window size, the dictionary size, and the symbol word-length, can be changed to suit the application. The proposed architecture is a high throughput and cost-effective architecture, and very suitable for wireless communication application

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Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on  (Volume:5 )

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