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Optimizing the number of parallel channels and the stage resolution in time interleaved pipeline A/D converters

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3 Author(s)
Sumanen, L. ; Lab. of Electron. Design, Helsinki Univ. of Technol., Espoo, Finland ; Waltari, M. ; Halonen, K.

In this paper the effect of the number of parallel channels and the stage resolution on the sample rate and power dissipation of time interleaved parallel pipeline analog-to-digital converters (ADC's) with identical stages are examined. Simple formulas are given to determine an optimum number of parallel channels and stage resolution for a given technology with respect to the conversion rate and current consumption. The formulas are applied for to 10 bit pipeline ADC using a standard 0.5 μm CMOS process parameters

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Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on  (Volume:5 )

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