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Browse Conference Publications > Circuits and Systems, 2000. P ... Help

An ALU design using a novel asynchronous pipeline architecture

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4 Author(s)
Tin-Yau Tang ; Dept. of Electron. Eng., Chinese Univ. of Hong Kong, Shatin, China ; Chiu-Sing Choy ; Butas, J. ; Cheong-Fat Chan

This paper presents a design of a 16-bit pipeline ALU. The ALU is implemented by using a novel asynchronous pipeline architecture. The architecture has simple handshake cells and these cells are embedded in the pipeline stage as normal logic cells. As a result, the speed of the ALU can be very fast

Published in:
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on  (Volume:5 )

Date of Conference: 2000

Page(s):
361 - 364 vol.5
Meeting Date :
28 May 2000-31 May 2000
Print ISBN:
0-7803-5482-6
INSPEC Accession Number:
6770200
Conference Location :
Geneva
Digital Object Identifier :
10.1109/ISCAS.2000.857439
Product Type:
Conference Publications

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