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An efficient algorithm for parametric fault simulation of monolithic IC's

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2 Author(s)
Strojwas, A.J. ; Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA ; Director, S.W.

An efficient methodology for performing fault simulation experiments as part of an IC failure diagnosis system is described. The methodology uses regression models that relate IC performance directly to process disturbances inherent in all IC fabrication processes. An efficient algorithm for establishing the structure of such models based on data obtained from coupled process and circuit simulators is developed. It selects a minimum number of significant input parameters and automatically establishes an optimum order polynomial regression model. Moreover. the regression models obtained contain information about the structure of the dependence of IC performances on the process disturbances, which can be coded in a dependency tree for each IC performance and used directly for diagnostic purposes. The algorithm belongs to the class of artificial neural network approaches and has been implemented in a program called MULREG (multilayer regression). Two examples of analyzing MULREG are given

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:10 ,  Issue: 8 )